1. Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved conductor structure.
2. Description of Related Art
U.S. application Ser. No. 08/098,044 filed Jul. 28, 1993 of G. Hong for "An Improved Mask ROM Process" now U.S. Pat. No. 5,308,777 describes a semiconductor device and a method of manufacturing a semiconductor device including forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. Then a gate oxide is formed on the surface of the substrate; a first conductive structure is formed on the gate oxide consisting essentially of polysilicon; an insulating structure is formed in contact with the first conductive structure; and then material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the work piece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.
A buried bit line ROM cell is by far the most competitive ROM structure of high density ROM memories because it is contactless and hence the cell size is smaller. The dimension of a cell is determined mainly by the pitches of the word line polysilicon structures employed to connect to the cells and the buried N+ bit lines. When the cell dimension shrinks, the buried bit line N+ doping needs to be reduced to avoid the problem of short channel punch through.
A device made with the low N+ concentration produced by the reduced level of doping is sensitive to the counter doping from P- type (boron) doping for programming in the channel region.
The boron implantation with a dose &gt;1.times.10E14 cm.sup.2 in the channel area for programming also goes into the source/drain buried N+ area with an As+implantation dose of about 1.times.10E15 cm.sup.2, which increases source/drain capacitance. Low buried bit line resistance is important because every cell will have a different bit line resistance to metal pick up contact (low resistance metallic line in contact with the contact opening.) For example, there will be one contact for every 32 cells.
An object of this invention is to make the ROM code implantation (boron for this case) into the center part of the channel area, which can achieve the goals of enhancing programming (turning the transistor off) and preventing the P+layer from encroaching upon or contacting with the N+ source/drain junction.
The problem solved by this invention is that in combination with post-metal-programming ROM process, ROM cells with high junction breakdown voltage, low junction capacitance and low buried N+ resistance for ROM product application which require higher breakdown voltage and higher speed circuits. The process is to implant programming P type boron ions into part of the channel region to turn the cell off and the boron ion implanted will not contact buried N+ drain/source regions.